1. Field of the Invention
The present invention relates to a semiconductor device having a trench gate structure and a method of manufacturing such a semiconductor device. In particular, the present invention relates to a power MOSFET.
2. Background Art
MOSFETs having a trench gate structure have been widely used as power MOS switches. Generally, a power MOS switch is required to operate at a high speed. The product (Ron×Qsw) of the ON resistance Ron and the switching charge Qsw of a MOSFET and the gate wiring resistance Rg serve as indicators of the high speed characteristic of a power MOS switch. The lower the values of these indicators, the better.
From this point of view, a semiconductor device, in which the wiring resistance Rg of the gate of a MOSFET is decreased, has been proposed as in, for example, Japanese Patent Laid-Open Publication No. 2001-345446. FIG. 15 shows the structure of such a semiconductor device. The conventional semiconductor device shown in FIG. 15 includes an N+ type semiconductor substrate 2 serving as a drain, an N− type epitaxial layer 4 formed on the N+ type semiconductor substrate 2, and a P type diffusion layer 6 formed on the N− type epitaxial layer 4. Furthermore, an N+ type diffusion layer 8 serving as a source is selectively formed on the P type diffusion layer 6. A trench 12 is formed through the N+ type diffusion layer 8 and the P type diffusion layer 6 so as to reach the N− type epitaxial layer 4. A gate dielectric film 14 is formed along the interior surface of the trench 12, i.e., on the side walls and the bottom of the trench 12. A gate electrode is formed inside the trench 12, the gate electrode being composed of a polycrystalline silicon layer 28 deposited to contact the gate dielectric film 14, and a silicide layer 29 deposited to completely fill in the trench 12.
However, in the semiconductor device disclosed in Japanese Patent Laid-Open Publication No. 2001-345446, a stress tends to occur at the interface between the polycrystalline silicon layer 28 and the silicide layer 29 at the bottom portion of the trench 12 when the silicide layer 29 is formed by the process of depositing a high melting point metal on the polycrystalline silicon layer 28 and performing a heat treatment thereby causing a reaction between the high melting point metal and polycrystalline silicon. This stress can be a cause of cracks generated in the P type diffusion layer 6 that serves as a channel and the N− type epitaxial layer 4. The cracks generated may lead to an increase in a leakage current Idss between the source and the drain, thereby degrading the reliability of the device.